4-bit PISO

Ring counter

A ring counter is a feedback shift register where the output of the shift register is coupled back to the input.[1]

It is also known as a Jonhson counter.

In ring counters, a bit pattern is repeated continuously, depending on the degree, as long as the clock signal is operating. Ring counters may also have a constant or variable serial input or a parallel pattern input.


A common use for shift registers is serial-to-parallel conversion. This is often necessary because it is easier to transfer signals in series and then restore the original byte format after the transfer. Shift registers can be used to form delay circuits without capacitance or inductance.

Bidirectional shift registers can be used to form stack circuits. SIPO registers are commonly used in microprocessor outputs when more output legs are needed than are available. This allows control of multiple binary devices.

Similarly, the PISO register is commonly used when a microprocessor would need more parallel inputs than the encapsulation allows. The various binary outputs are connected to the PISO input, and then the corresponding bits are fed serially into the microprocessor.

Shift registers can also be used to widen a pulse. Here the timing of the pulse does not depend on analog elements, only on the accuracy of the clock signal. In early computers, the shift register was part of the data processing unit. It was used in the arithmetic logic unit (ALU) for binary operations.

In early computers, it was used as a delay line memory, where the signal applied to the input was fed back to the input after the appropriate offset (delay). In today's computers, this is the updatable memory.

Structure and operation

Restarting the watchdog

The watchdog timer can be reset[2][3] by writing to a watchdog figuratio bt control port. Alternatively, in microcontrollers that have a built-in watchdog timer, the timer is sometimes reset by executing a special machine language instruction or by setting a specific bit in a register. An example of this is the CLRWDT (clear watchdog timer) instruction, which is included in the instruction set of some PIC microcontrollers.

In computers running an operating system, the watchdog reset is invoked via a driver. For example, in the Linux operating system, a user-level program restarts the timer figuratio bt using the watchdog driver, usually by writing a null character to /dev/watchdog. The driver, which separates the hardware from the user-level programs, is also used to configure the timeout and to start and stop the timer.

Single-step watchdog

Watchdog timers come in many configurations and many allow their configuration to be changed. Microcontrollers often include a built-in watchdog timer. In other computers, the watchdog is located in a chip nearby, either directly connected to the processor or on an external expansion card in the computer. The watchdog and the processor can operate on the same clock, as shown in the block diagram below, or on independent clocks.

Block diagram of a simple single-step watchdog timer. The common clock signal is typical of the basic watchdog timers found in simple microcontrollers.

Multi-step watchdog

Sometimes two or more timers are figuratio bt used to form a multi-stage watchdog timer, where each timer is called a timer stage or simply a stage. For example, the block diagram below shows a three-step watchdog. In a multi-stage watchdog, the processor only starts the first stage. When the timeout of the first stage expires, the recovery operation starts and the next stage is started. When the last stage timeout expires, the recovery operation is initiated, but no new stage is started. In general, a single-stage watchdog is used to simply restart the computer, while multi-stage watchdogs perform recovery operations in sequence, with the computer restarting after the last stage.

A three-step watchdog timer.

Time intervals

Time intervals can be fixed or figuratio bt programmable values. Some watchdog timers allow you to program the time intervals so that you can choose between a few different values. In others, the interval can be programmed to any value. In general, watchdog time intervals range from ten milliseconds to one minute or more. In a multi-step watchdog, each timer has its own unique time interval.

Recovery operations

The watchdog timer can initiate various types of recovery operations, including maskable interrupts, non-maskable interrupts, processor restarts, fail-safe activation, or combinations of these. Depending on the configuration, the type of recovery operation or operations that the watchdog can trigger may be fixed or figuratio bt programmable. Some computers require a pulse signal to restart the processor. In such cases, the watchdog usually triggers a processor restart by activating an internal or external pulse generator, which in turn generates the necessary restart signals.[3]

In embedded systems and control systems, watchdog timers are often used to activate fail-safe circuits. When activated, the fail-safe circuit forces all control outputs to a safe state (e.g., shuts down motors, heaters, and high voltage) to avoid damage and equipment degradation while the fault persists. In a two-stage figuratio bt watchdog, the first timer is often used to activate the fail-safe state and start the second timer stage; the second stage restarts the computer if the fault cannot be corrected before the timer expires.

Watchdog timers are often used to start recording system state information or debugging information to a backing store (the former can be useful for debugging,[3] the latter for determining the cause of a failure). In such cases, a second timer - started after the first timer has elapsed - is usually used to restart the computer later, after sufficient time has been allowed to capture the data. This ensures that the computer will restart even if the capture process fails.

A two-step watchdog timer.

For example, the figure above shows the likely structure of a two-step watchdog timer. During normal operation, the computer periodically restarts the first timer to avoid timeouts. If the computer is unable to restart the first timer (e.g. due to hardware failure or programming error), it will time out. This event will start the second timer, and at the same time notify the computer (via a non-maskable interrupt) that a restart is about to start. The computer may attempt to record status information and/or debug information until the second timer expires. The computer will restart when the second timer expires.


A computer system is usually designed so that the watchdog timer is only restarted when the computer determines that the system is operational. The computer determines if the system is operational by running one or more debug tests and only restarts if all tests are successful. In a computer running an operating system and multiple processes, a simple test is not sufficient to guarantee normal operation, since it cannot detect a small error, and therefore allows watchdog to restart even if the system is malfunctioning.

For example, in the case of the Linux operating system, the user-level watchdog daemon periodically restarts the watchdog without running any tests. As long as the daemon is running normally, it protects the system from severe system crashes, such as kernel panics. To detect less serious failures, the daemon[4] can be configured to run tests covering resource availability (e.g. sufficient memory and file writes, reasonable processor time) and evidence of expected process activity (e.g. running system daemons, updating specific files), overheating and network activity, and system-specific test scripts or programs[5].

In the event of a failed test, the Linux watchdog daemon may attempt a software-initiated reboot, which may be preferable to a hardware reboot because the file system is safely disconnected and error information is logged. However, it is essential to provide a hardware timer, as software reboots may not work in the event of a number of errors. In effect, this is a two-stage watchdog, with the first step being a software restart and the second a hardware restart.

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